The present invention relates to circuitry and methods for testing a memory device More particularly, the present invention provides circuitry and methods for testing memory cells of an edge of an array of memory cells.
Referring to FIG. 1, a known exemplary memory cell 102 comprises capacitor 104 and a transistor 108 coupled in series therewith as a switch for selectively accessing the capacitor. One plate, or electrode 101, of the capacitor is coupled to a common node. The other electrode 103 of the capacitor serves as a storage electrode for the memory cell. The transistor 108 typically comprises a MOSFET transistor and has its gateable channel electrically coupled between the storage electrode 103 of the capacitor and a bitline 106.
For a semiconductor memory device, e.g., a Dynamic Random Access Memory (DRAM), referencing FIGS. 2A, 2B, a plurality of memory cells 102 are arranged in rows and columns, e.g., as an x-y grid, to provide an array 200 of memory cells. Conductive bitlines 105, 106 extend a length of the array and connect bitline contacts 122 of respective columns. Wordlines 110 extend widths of the array and connect control terminals of the access transistors of their respective rows. Known address decode circuitry 109, 107 determines, in accordance with supplied address data, select bitlines and wordlines upon which to propagate data and enable signals respectively.
Further referencing FIGS. 2A, 2B, known decode circuitry 109 drives wordlines 110 in accordance with received address data. When activated by the decode circuitry, a wordline propagates an enable signal for enabling access transistors of its row of memory cells. Once the access transistors are enabled, data of the true or complementary bitlines 105, 106 respectively, is transferred provide data for transfer into capacitors of the memory cells of the selected row. Alternatively, during a read operation, data is transferred from the capacitors to the bitlines.
Within the present disclosure, the terms xe2x80x9conexe2x80x9d and xe2x80x9czeroxe2x80x9d will refer to high and low data or logic levels respectively. Additionally, an enable signal may be thought of as enabling when active high. Notwithstanding the above, the present disclosure is deemed to encompass reverse or complementary perspectives thereof.
Further referencing FIGS. 2A, 2B, known sense amplifiers 114 sense and differentially amplify voltage levels of the true and complementary bitlines 105, 106 in accordance with data provided thereto. Know input/output buffers and column decoders 107 decode address data and propagate data upon select bitlines as determined by the address data. Known equilibration circuits 115 equilibrate the true and complementary bitlines 105, 106 to an equilibration bias level, i.e., of equilibration node 117, before the sense amplifiers are enabled. Equilibration node 117 is typically biased with the intermediate voltage level (e.g., DVC2). Known bus or supply circuitry distribute an upper voltage, e.g., VCC, lower voltage, e.g., Ground, and the intermediate voltage, e.g., Vcc/2, about the memory device.
In normal operation, a high data level is stored within a memory cell by biasing a bitline with an upper logic level, e.g., Vcc, and activating a wordline 110 with an enable signal for enabling the memory cell""s access transistor and transferring the upper voltage level (Vcc) of the bitline into the memory cell""s storage electrode. Assuming an intermediate voltage bias at the common electrode 101 of, e.g., Vcc2, a positive voltage difference, e.g.,+Vcc/2, is provided for storage between the storage and common electrodes of the memory cell""s capacitor 104. Thereafter, the wordline is deactivated for disabling the access transistor and isolating the storage electrode from the bitline. Likewise, a low data level may be stored within the memory cell using a similar procedure but with the bitline biased at the lower logic level, e.g., ground, during the write cycle, thereby providing a negative voltage difference, e.g.,xe2x88x92Vcc/2, between the storage and common electrodes of the capacitor.
It will be understood that the present description of a known exemplary dynamic random access memory (DRAM) and its operation is meant to provide a general understanding of a DRAM and is not meant to provide a complete description thereof.
Further referencing FIG. 2B, two separate storage node contacts at distal ends of active regions 120 are electrically coupled to the storage electrodes of respective memory cell capacitors. Accordingly, one of the cells employs one-half of active region 120 while the other, adjacent cell employs the other half of the active region. Two different row wordlines 110 overlap respective portions of active region 120 and form transistor gates thereover for controlling channels of their respective access transistors, which in turn enable selective coupling of the memory cell capacitors to a shared column bitline 105 (106) by way of a bitline contact 122 between the two wordlines.
FIG. 3 portrays, in simplified view, exemplary storage node electrodes of memory cell capacitors of a memory array. Wordlines 110 are schematically illustrated in order to facilitate an understanding of placements of the storage electrodes. During fabrication of the memory array, a defect 130 may result between adjacent capacitors, for example, between storage electrodes 132 and 134. It is theorized that such defect 130 could be caused, for example, by residual polysilicon particles settling between the electrodes during fabrication of the array. In schematic representation, referencing FIG. 4, defect 130 provides a resistive path between the storage electrodes 132, 134 of neighboring capacitors 104A and 104B. Accordingly, data of a xe2x80x9conexe2x80x9d level stored at capacitor 104A might bleed-off and into a neighboring capacitor 104B so as to potentially corrupt their data contents, assuming capacitor 104B stores a xe2x80x9czeroxe2x80x9d level.
During the manufacture of semiconductor memory, known tests screen the memory for defects and assure quality of shipped product. For a memory device comprising, for example, a dynamic random access memory (DRAM), one known test comprises writing a checker-board pattern of dataxe2x80x94e.g., alternating 1""s and 0""sxe2x80x94into memory cells of the array in order to check the cell-to-cell isolation between neighboring memory cells. U.S. Pat. No. 5,657,284, entitled xe2x80x9cApparatus and Method for Testing Defects Between Memory Cells In Packaged Semiconductor Memory Devices,xe2x80x9d discloses one such exemplary test method that writes alternating xe2x80x9conexe2x80x9d and xe2x80x9czeroxe2x80x9d data levels of the checkerboard test pattern into an array of memory cells. When writing, for example, a designated xe2x80x9conexe2x80x9d cell, a high data level is applied to the storage electrode of the designated xe2x80x9conexe2x80x9d cell for a duration sufficient to bring-out (or effect a current flow through) a potential short-circuit defect to an adjacent xe2x80x9czeroxe2x80x9d cell, i.e., of a zero data level. Checking the values of the adjacent xe2x80x9czeroxe2x80x9d cells after writing the designated xe2x80x9conexe2x80x9d cell enables determination of potential cell-to-cell defects. U.S. Pat. No. 5,657,284 is assigned to the assignee of the present application and is incorporated herein by reference.
It is known to provide dummy cells around the periphery of a memory array in order to assist process uniformity during fabrication of the array of memory cells. Referencing FIG. 5, the known checkerboard pattern of test data within the array of memory cells stresses and tests the cell-to-cell isolation between inner cells of the array. However, memory cells at the periphery of the memory array receive stressing and testing relative to the inner cells of the array without significant testing external thereto. The known dummy cells of the exemplary prior art which neighbor a peripheral row of the array, have their wordline grounded (See FIG. 2B) to disable their associated access transistors (N-channel MOSFETs) and isolate the storage electrodes of the dummy cells from respective true or complementary bitlines 105, 106. Being isolated, the storage electrodes of the dummy cells are not able to receive full logic level, stress voltages for stressing the memory cells of the array""s peripheral row.
Referencing FIG. 6, capacitor 202 of a dummy cell neighbors capacitor 104 of a periphery of memory array 200. Transistor 204 of the dummy cell has its channel electrically coupled between the storage electrode and an intermediate supply, e.g., of voltage DVC2, via bitline 203. Again, but with reference to this simplified schematic illustration of FIG. 6, the gate terminals of access transistors 204 of the exemplary prior art dummy cells adjacent a peripheral row of the memory array, are coupled to ground via wordline RDC. With their gates grounded, access transistors 204 are biased in xe2x80x9cOFFxe2x80x9d states for isolating the storage electrodes of capacitors 202. Additionally, dummy cells adjacent a peripheral column of the array have their bitline 203 coupled to an intermediate voltage DVC2, so as to limit residual currents which might otherwise result from a defective dummy cell. With only an intermediate voltage bias available to these dummy cells, full xe2x80x9c1xe2x80x9dxe2x88x92xe2x80x9c0xe2x80x9d voltage levels are not available to the dummy cells for stressing memory cells of the peripheral column. Thus, memory cells of the array periphery are not able to be stressed to the same extent by which the array""s inner cells may be subjected, which inner cells can be configured to achieve full xe2x80x9c1xe2x80x9dxe2x88x92xe2x80x9c0xe2x80x9d (i.e., Vccxe2x88x92Ground) voltage differences therebetween.
What is needed, therefore, is a method of stressing and testing peripheral cells of a memory array. The present invention recognizes this need and proposes solutions thereto.
In accordance with an embodiment of the present invention, a memory device comprises an array of memory cells having at least one edge. Test circuitry is selectively configurable to interchangeably couple a dummy cell, which neighbors a memory cell at an edge of the array, to a select one of a plurality of different voltages. In a preferred embodiment, the test circuitry is configurable to selectively couple the dummy cell to one of an upper, lower or intermediate supply bus.
In accordance with another embodiment of the present invention, a method of testing a memory cell at an edge of an array comprises writing the edge memory cell with a first logic level. A dummy cell adjacent the edge memory cell is electrically biased with a voltage opposite that of the first logic level. Next, the memory cell is read and its contents compared to that previously written therein. Preferably, the dummy cell remains biased while the memory cell is read.
In a further exemplary embodiment of the present invention, edge-memory cells of a peripheral row are tested. Dummy cells are disposed adjacent the edge memory cells, and, in accordance with one aspect of this embodiment, share bitline contacts and bitlines in common with the edge memory cells. Data of first logic levels are written into the memory cells of the peripheral row while access transistors of the dummy cells remain disabled. Upon writing data into the peripheral row, the access transistors of the peripheral row are disabled. An enable signal is then provided to a dummy wordline for enabling access transistors of the dummy cells. Stress data is applied to the dummy cells of value opposite the first logic levels. Next, the access transistors of the dummy cells are disabled and data read from the memory cells of the peripheral row for comparison against that previously stored therein.
An alternative exemplary embodiment employs dummy cells adjacent a peripheral row of memory cells, which dummy cells and peripheral row of memory cells do not share bitlines and bitline contacts. Instead, the dummy cells employ contacts and bitlines separate those of the peripheral row. For this embodiment, bitlines drivers associated with the dummy cells are configured to drive respective bitlines with levels opposite the levels that were provided to the peripheral row of memory cells. A dummy wordline driver is configured to enable access transistors of the dummy cells so capacitors of the dummy cells receive the voltage level biasing of the bitlines. Preferably, the dummy cell capacitors remain coupled to the bitlines and continue to receive their bitline biasing while contents of the memory cells are read.
In accordance with another exemplary embodiment, memory cells of a peripheral column of an array are tested. Alternate pairs of wordlines are driven for simultaneously writing data from a shared bitline into each memory cell of the peripheral column. Others of the alternate pairs of wordlines are driven for enabling access transistors of the dummy cells while providing a voltage level opposite that which was provided to the peripheral column to a bitline of the dummy cells. Storage electrodes of the dummy cell capacitors receive the bias level of the dummy bitline for stressing regions between the dummy cells and memory cells of the peripheral column. Thereafter, data is read from the memory cells of the peripheral column for comparison against that previously stored therein. Preferably, the capacitors of the dummy cells remain coupled to the dummy bitline and continue to receive the stress biasing while the memory cells of the peripheral column are read.
These and other features of the present invention will become more fully apparent in the following description and independent claims, or may be learned by practice of the invention as set forth hereinafter.